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Thermistor materials utilizing single-crystalline silicon-germanium alloys, embedded in lowly doped silicon are very suitable for bolometer applications since the inherent noise level is low and exhibits a normal 1/f spectrum. A thermal coefficient of resistance (TCR) value of at least 2%/K can be obtained at room temperature and the performance is directly comparable with nonsemiconductor materials...
This work presents thermal and electrical characterization of SiGe/Si multi-quantum wells (MQWs) with different layer profiles in complete bolometer structures. The thermal property of the bolometers was studied by measuring thermal coefficient of resistivity (TCR) through I-V curves for five temperatures (25, 40, 55, 80 and 100degC) and for four different pixel areas. The results show a strong dependency...
The influence of chip layout and architecture on the pattern dependency of selective epitaxy of B-doped SiGe layers has been studied. The variations of Ge-, B-content, and growth rate have been investigated locally within a wafer and globally from wafer to wafer. The results are described by the gas depletion theory. Methods to control the variation of layer profile are suggested.
Strained Si HBTs have been demonstrated for the first time with a maximum current gain (beta) of 3700 using a relaxed Si0.85Ge0.15 virtual substrate, Si0.7Ge0.3 base and strained Si emitter. This represents 10times and 27times larger gain compared with pseudomorphic SiGe HBTs and Si control BJTs which were manufactured in parallel and had current gains of 334 and 135, respectively. The strained Si...
We present a comprehensive study of biaxially strained (up to ~3 GPa stress) Si nMOSFETs down to 80 nm gatelength. Well behaved 80 nm devices with expected strain-induced electrical enhancement were demonstrated. Special emphasis was put on investigation of substrate junction leakage and source to drain leakage. In-situ doped wells and channel profiles demonstrated superior substrate junction leakage...
In this paper the selective epitaxy of B- and P-doped SiGe layers on either HCl-etched or un-processed Si surfaces for S/D application in CMOS structures have been investigated. The study has focused on how to obtain high quality layers and tackle subjects e.g. dopant incorporation and defect generation in these layers
An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. Implementation of high kappa gate dielectrics is presented and device performance is demonstrated for TiN metal gate surface channel SiGe MOSFETs with a gate stack based on ALD-formed HfO2/Al2O3. Low frequency noise properties for...
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