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For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were...
1.2 kV SiC buried grid junction barrier Schottky (BG-JBS) diodes are demonstrated. The design considerations for high temperature applications are investigated. The design is optimized in terms of doping concentration and thickness of the epilayers, as well as grid size and spacing dimensions, in order to obtain low on-resistance and reasonable leakage current even at high temperatures. The device...
This paper presents promising current-voltage characteristics of semiconductor-insulator-graphene tunnel diodes as the hot-electron injection unit in graphene base transistors (GBTs). We propose that by using a bilayer tunnel barrier one can effectively suppress the defect mediated carrier transport while enhancing the hot-electron emission through Fowler-Nordheim tunneling (FNT) and step tunneling...
We report a first study of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs). Our results show that HCD in GFETs is recoverable, similarly to the bias-temperature instability (BTI). Depending on the top gate bias polarity, the presence of HCD may either accelerate or suppress BTI. Contrary to BTI, which mainly results in a change of the charged trap density in the oxide, HCD...
We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C–350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate...
We study the impact of hot-carrier degradation (HCD) on the performance of graphene field-effect transistors (GFETs) for different polarities of HC and bias stress. Our results show that the impact of HCD consists in a change of both charged defect density and carrier mobility. At the same time, the mobility degradation agrees with an attractive/repulsive scattering asymmetry and can be understood...
We propose a graphene transfer method based on chemical vapor deposited (CVD) graphene grown on copper foils. This transfer method utilizes a combination of a silicone elastomer (PDMS) and different intermediate polymer layers depending on the process requirements. We use polystyrene and polystyrene/photoresist intermediary layers for dry and wet graphene release. PMMA intermediary layer is applied...
We present a detailed analysis of the bias-temperature instability (BTI) of single-layer graphene field-effect transistors (GFETs). We demonstrate that the dynamics can be systematically studied when the degradation is expressed in terms of a Dirac point voltage shift. Under these prerequisites it is possible to understand and benchmark both NBTI and PBTI using models previously developed for Si technologies...
We report on a wafer scale fabrication of graphene based field effect transistors (GFETs) for use in future radio frequency (RF) and sensor applications. The process is also almost entirely CMOS compatible and uses a scalable graphene transfer method that can be incorporated in standard CMOS back end of the line (BEOL) process flows. Such a process can be used to integrate high speed GFET devices...
Integration of high-k interfacial layers in CMOS technology has been proposed to overcome the scaling limitations of the SiOx/HfO2 dielectric stack. Candidate high-k interfacial layers have to be compatible with strict requirements in terms of EOT, inversion layer mobility, threshold voltage control and device reliability. We have previously demonstrated a CMOS-compatible process for integration of...
We present a sidewall transfer lithography (STL) process to fabricate silicon nanowires using the CMOS compatible materials SiO2, SiN and α-Si. The STL process is implemented using a single cluster tool for reactive ion etching (RIE) and plasma enhanced chemical vapor deposition (PECVD) with a maximum process temperature of 400 °C. Using three lithography masks, single and multiple silicon nanowires...
This work describes a strained germanium on insulator (GeOI) fabrication process using wafer bonding and etch-back techniques. The strained Ge layer is fabricated epitaxially using reduced pressure chemical vapor deposition (RPCVD). The strained Ge is grown pseudomorphic on top of a partially relaxed Si0.66Ge0.34 layer. Wafer bonding is performed at room temperature without post-anneal processes and...
Pressure sensors based on suspended graphene membranes have shown extraordinary sensitivity for uniaxial strains, which originates from graphene's unique electrical and mechanical properties and thinness [1]. This work compares through both theory and experiment the effect of cavity shape and size on the sensitivity of piezoresistive pressure sensors based on suspended graphene membranes. Further,...
Low-frequency noise of HfO2/TiN nMOSFETs with different SiOx interfacial layer (IL) thicknesses is presented. It is observed that chemically formed thin ILs (0.4 nm, 0.45 nm and 0.5 nm) show a noise level close to a reference thermal IL(1 nm). This is shown to relate to the dominant contribution of the high-k HfO2 traps in comparison to the IL traps. The average extracted values for effective trap...
The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-k/metal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500–900 °C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the...
We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of 32 by 32 pixel matrix (1024 pixels or test sites) and 8 input-output (I/O) pins. In each pixel single crystalline SiNW with 60 by 20 nm cross-section area is defined using sidewall transfer lithography (STL) in the SOI layer. The key advantage of the design is that 1024 individual...
This review will discuss the in-situ surface engineering of active channel surfaces prior to or during the ALD high-k/metal gate deposition process. We will show that by carefully choosing ALD in-situ pre-treatment methods and precursor chemistries relevant electrical properties for future high-k dielectrics can be improved. Different high-k dielectrics such as Hafnium-Oxide (HfO2), Aluminum-Oxide...
In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for microelectronics integration: bottom gates with ultra-thin (2nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is...
Graphene has caught the attention of the electronic device community as a potential future option for More Moore and More Than Moore devices and applications. This is owed to its remarkable material properties, which include ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs in pristine graphene. Furthermore, standard CMOS technology may be...
The future manufacturability of graphene devices depends on the availability of large-scale graphene fabrication methods. While chemical vapor deposition and epitaxy from silicon carbide both promise scalability, they are not (yet) fully compatible with silicon technology. Direct growth of graphene on insulating substrates would be a major step, but is still at a very early stage [1]. This has implications...
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