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This paper introduces a novel FinFET based domino logic, which exploits the exclusive property of the FinFET device (capacitive coupling between front-gate and back-gate in a four-terminal (4T) FinFET) to simultaneously achieve higher performance and lower power consumption. Using a new implementation of the resistive gate, the keeper device is made weaker at the beginning of the evaluation phase...
A 0.15 /spl mu/m CMOS technology integrating W/WNx/polysilicon gate electrodes and Ti silicided source/drain diffusions is presented in this paper. Gate electrodes with sheet resistance as low as 1.6 /spl Omega//sq. and Ti silicided source/drain diffusions of 3.6 /spl Omega//sq. are realized. As a result, both the gate RC delay and parasitic source/drain resistance are minimized and high circuit performance...
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