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To enable autonomous driving, a computing stack must simultaneously ensure high performance, consume minimal power, and have low thermal dissipation—all at an acceptable cost. An architecture that matches workload to computing units and implements task time-sharing can meet these requirements.
Regenerative fuel cells (RFC) have become an attractive technology for energy storage systems due to their high energy density and lower end-of-life disposal concerns. However, high efficiency design of power conditioning unit (PCU) for RFC becomes challenging due to their asymmetrical current-power characteristics that are dependent on the operation mode (energy storage / energy supply). This paper...
Multi-core may afford the computation capacity for the computation-intensive tasks, such as machine learning. In such a chip, the inter-cores communication is one of the greatest challenges. A synthesizable wormhole router was proposed for the emerging inter-cores communication scheme, i.e. network-on-chip (NoC). The proposed router not only offers common configurable parameters including buffers,...
Design of high-performance router is one of the greatest challenges facing Network-on-Chip (NoC). A 5-stage pipelining scheme was proposed for wormhole router in NoC. It originates from the canonical 4-stage pipelining scheme, and had the longest stage for virtual-channel allocation in the ancestor split into two stages. The 5-stage pipelining scheme may boost the maximum frequency of the router and...
The trusted network connect (TNC) is based on the double concepts of integrity and identity. The policy enforcement point (PEP) in TNC architecture is deeply studied and powerful broadband remote access server (BRAS) is also applied into the architecture. The new BRAS model is able to set up access control rules in accordance with the level of trust, filter traffic according to filtering rules and...
The computing power of microprocessors has exponentially increased in the past few decades, so the support to compute intensive multimedia applications has increased too. With such improved computing power, memory subsystem deficiency becomes the major barrier to support video decoder on the Digital Signal Processor (DSP). H.264/AVC becomes the next generation of video codec for embedded systems....
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