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This paper presents a novel electric/electronic (E/E) architecture simulator that allows the evaluation of design alternatives during early stages of the automotive development process. The simulation framework performs a joint power/performance evaluation for different partitionings of functional chains on a given multi-ECU technical architecture. The high-level modeling approach results in a short...
Host-compiled software simulation has become a popular method to accelerate iterative system-level design space explorations of multiprocessor systems-on-chip (MPSoCs) by abstracting the internal microarchitecture of cores. However, current approaches do not consider out-of-order processor architectures, which are emerging in the embedded system domain. Out-of-order processors exhibit complex timing...
The exploration of the design space for complex hardware-software systems requires accurate models for the system components, which are often not available in early design phases, resulting in error-prone resource estimations. For a HWSW system with a finite set of design points, we present an analytical approach to evaluate the quality of a distinctive design point choice. Our approach enables the...
Through Silicon Vias (TSVs) are the method of choice to realize vertical connections between different chip layers in three dimensional Integrated Circuits (3D-ICs). These TSVs offer a fast connection and due to their short wire length, only a small capacitive load to the driving circuitry. On the other hand TSVs consume a relative large amount of chip area and as TSV-count increases the overall yield...
Tiled manycore architectures have become dominant for the integration of tens or even a hundred processor cores on a chip. While commercial products are increasingly available, research on the hardware of such platforms and especially prototyping often rely on building such a platform from scratch or is bound to abstract simulation. In this paper we present the Open Tiled Manycore System-on-Chip (Op-TiMSoC)...
Cyber Physical Systems (CPS) design expands the horizon of traditional hardware/software systems engineering into the specifics of natural sciences such as physics or bio-chemistry. This is a new quality and inherent challenge of CPS since interdisciplinary skills, methods, tools and design flows, which originally werent even considered for mutual awareness, should now be linked, inter-work with each...
When migrating to future technology nodes, dependability becomes a major design problem as variability, aging and susceptibility to soft errors increase. The purpose of this program is to research cross-layer solutions that address the physical problems at system-level i.e. at hardware-level, operating system level, application level etc. The goals and an overview of the DFG SPP 1500 research program...
Networks-on-Chip have shown their scalability for future many-core systems on chip. In real world scenarios, concurrent applications with different QoS requirements affect each other through overlapping communication. Therefore computation resources may not be efficiently utilized because the required communication resources are already occupied. Hence, an efficient resource management strategy is...
MPSoCs need to integrate self-x properties in order to get rid of the worst-case design style which is no longer affordable in large SoCs. Integrating self-x properties in SoCs is possible through a monitoring interconnect which carries monitor information to evaluators that decide on actions that will tune the SoC operation mode.We have designed a customized interconnect for SoC monitoring/actuation...
Manycore platforms with tens and even up to hundreds of processing cores per chip are becoming a commercial reality and are subject of intensified research. This concept paper describes work in progress on the applicability of HW supported communication and processing virtualization on regular structured, tiled manycore architectures for the benefit of improved fault tolerance against transient and...
This paper introduces a scalable hardware and software platform applicable for demonstrating the benefits of the invasive computing paradigm. The hardware architecture consists of a heterogeneous, tile-based manycore structure while the software architecture comprises a multi-agent management layer underpinned by distributed runtime and OS services. The necessity for invasive-specific hardware assist...
The trend of current and future domain-specific MPSoCs towards heterogeneous and tiled architectures as well as the increasing number of cores on a single chip impedes the design and the parallel programming of such computing systems. To tackle this problem a new computing paradigm called invasive computing has recently been proposed. Here, the workload and its distribution are not known at compile-time...
The case for developing and using virtual platforms (VPs) has now been made. If developers of complex HW/SW systems are not using VPs for their current design, complexity of next generation designs demands for their adoption. In addition, the users of these complex systems are asking either for virtual or real platforms in order to develop and validate the software that runs on them, in context with...
One of the major challenges of future many-core architectures is the efficient utilization of the abundance of computing power. Invasive computing provides a computing paradigm wherein applications can economically use the available compute resources. Applications can expand and shrink on demand depending on their thread level parallelism and resource availability. In this paper we present an analytical...
Advanced out-of-order processors exhibit complex dynamic behavior. Therefore, they are difficult to model at abstraction levels higher than cycle-accurate instruction set simulators (ISS's). Conventional compiled simulation techniques have been widely used for fast performance estimation. However, they assume static time intervals between memory accesses and do not consider diverse behavior of out-of-order...
The effects of single event upsets (SEU) are becoming increasingly important to circuit designers. Exact and detailed error rate estimations are needed to determine a system's level of reliability. The architectural vulnerability factor (AVF) is a measure for the relative reliability of a circuit. In this paper we outline the properties of several known approaches such as statistical testing (fault...
Future manycore Systems-on-Chip will integrate tens or even hundreds of cores. Tiled architectures have come to the focus of research and industry. Such platforms integrate processing cores in clusters and connect those ‘tiles’ with a global interconnect. Message passing programming models are favored to program such complex distributed memory systems. A significant performance overhead is involved...
The paper presents an overview of a major research project on dependable embedded systems that has started in Fall 2010 and is running for a projected duration of six years. Aim is a ‘dependability co-design’ that spans various levels of abstraction in the design process of embedded systems starting from gate level through operating system, applications software to system architecture. In addition,...
Due to the growing complexity of multiprocessor systems-on-chip (MPSoCs), there is an increasing demand on efficient design space exploration techniques. In addition to the analysis of diverse hardware architectures, these techniques should assist the designer in the flexible evaluation of various scheduling policies and application mappings while taking effects of the shared on-chip communication...
With the transition from buses to on-chip networks in SoCs the problem of deadlocks in on-chip interconnects arises. Deadlocks can be caused by routing cycles in the network, or by message dependencies, even if the network itself is actually free of routing cycles. Two basic approaches to counter message dependent deadlocks exist: deadlock avoidance, which is most popular in NoCs, and deadlock recovery,...
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