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The need for faster and more energy efficient computing has led us to the multicore era with distributed shared memory hierarchies. The primary goal is to distribute parallel tasks onto multiple processing elements to collectively achieve shorter execution times at lower frequencies and supply voltages when compared to a single-core architecture. Major challenges of this approach are how to achieve...
In an era of continuously shrinking technology and escalating power density, Multiprocessor System on Chips (MPSoCs) suffer from a growing prominence of device defects and increase of dependability-related issues. This paper tackles the dependability challenge by suggesting an adaptive reliability enhancement strategy for multicore systems. We dynamically adapt the reliability enhancement to the actual...
Locks are widely used as a synchronization method to guarantee the mutual exclusion for accesses to shared resources in multi-core embedded systems. They have been studied for years to improve performance, fairness, predictability etc. and a variety of lock implementations optimized for different scenarios have been proposed. In practice, applying an appropriate lock type to a specific scenario is...
Self-awareness has been used in many research fields in order to add autonomy to computing systems. In automotive systems, we face several system layers that must be enriched with self-awareness to build truly autonomous vehicles. This includes functional aspects like autonomous driving itself, its integration on the hardware/software platform, and among others dependability, real-time, and security...
Content aware networking will be an integral feature in the next generation Residential Gateway Routers (RGR). Signature matching is the most time critical operation in content aware networking. Improving broadband speed necessitates the need for hardware acceleration of signature matching to manage and safeguard all the Internet of Things (IOT) clients connected to the smart home. Deterministic Finite...
Software diagnosis on MPSoCs, the process of finding functional bugs or performance inefficiencies in complex hardware-software systems, is challenging. As both software and hardware complexity grow, the software observability decreases. At the same time, understanding the intended software behavior has become more difficult. We present an integrated approach which combines domain-specific representations...
FPGAs (Field Programmable Gate Arrays) are making their way into data centers (DC). They are used as accelerators to boost the compute power of individual server nodes and to improve the overall power efficiency. Meanwhile, DC infrastructures are being redesigned to pack ever more compute capacity into the same volume and power envelops. This redesign leads to the disaggregation of the server and...
We introduce the idea of an Information Processing Factory as a step towards autonomous manycore platforms in Cyber-Physical Systems (CPS) and the Internet of Things (IoT). It represents a paradigm shift in platform design moving long term, with robust and independent platform operation in the focus of platform-centric design rather than existing semiconductor device or software technology, as mostly...
PCI Express (PCIe) Single Root I/O Virtualization (SR-IOV) enables low latency and high performance virtualization of I/O devices. It has been embraced in cloud computing and is considered a promising foundation for sharing I/O in future multi-core embedded and mixed-criticality systems. Unfortunately, SR-IOV is vulnerable to Denial-of-Service (DoS) attacks, which cause performance interference. For...
In modern symmetrical chip multiprocessor (CMP) architecture, problems in cache coherence, context switch overheads and serialized code bottleneck are major causes of excessive computing power dissipation in the application of simultaneous multithreading (SMT) technique. This research models and manages above-mentioned problems based on user application usage patterns identified in a mobile computing...
Thread mapping is typically performed as an integral part of cooperative or pre-emptive operating system (OS) scheduling in order to share the processor core(s) among competing applications. Schedulers usually follow a single-objective performance optimization, such as maximizing core utilization or satisfying deadlines by the prioritization of threads. Meeting multiple orthogonal objectives, like...
Network-on-Chip (NoC) are well-established for scalable on-chip communication, but technology generations of 22~nm and below, as well as aggressive voltage scaling to reduce NoC power consumption, introduce new variability challenges resulting in errors on wires and registers. Based on the probabilities of single bit flips, this paper focuses on the expected end-to-end packet error probabilities in...
Communication requirements in automotive electronics are steadily increasing. To satisfy this demand and enable future automotive embedded architectures, new interconnect technologies are needed. Audio Video Bridging (AVB) Ethernet is a promising candidate to accomplish this as it features time-sensitive and synchronous communication in combination with high bit rates. However, there is a lack of...
Safety-critical systems and in particular mixed-criticality systems require spatial and temporal separation for their hosted applications and functionalities. Additional constraints are using Commercial Off -- The -- Shelf (COTS) components, portability and determinism. These items are required for economic success for products with low piece numbers and long life-cycles like aircraft. Available embedded...
FPGAs (Field Programmable Gate Arrays) are making their way into data centers (DCs) and are used to offload and accelerate specific services, but they are not yet available to cloud users. This puts the cloud deployment of compute-intensive workloads at a disadvantage compared with on-site infrastructure installations, where the performance and energy efficiency of FPGAs are increasingly being exploited...
Automotive embedded systems are highly complex and historically grown networks of single-core based control units. Due to space limitations and wiring complexity, the scalability of current architectures is limited. It can be overcome by consolidating multiple currently distributed functions onto shared multi-core platforms. Additionally, virtualization can be used to isolate these functions in separate...
Dependability and fault tolerance will play an ever increasing role when using future technology nodes. The paper presents a fault-tolerance strategy for invasive networks on chip (i-NoC). The strategy focuses on permanent faults, resulting from either process fluctuations or aging effects and briefly outlines counter measurements against transient faults. We propose a scalable scheme for detection...
Single Root I/O Virtualization (SR-IOV) is an extension to the PCI Express (PCIe) standard that allows virtual machines (VMs) to directly access shared I/O devices without host involvement. This enabled SR-IOV to become the best-performing solution for virtual I/O to date, which lead to its commercial adoption, e.g., In the Amazon EC2. On the downside, a malicious VM can exploit the direct access...
Dynamically expendable real-time systems are an essential improvement over current future automotive E/E architectures. New functions and applications like automated driving or the subsequent activation of features require a different approach. This also applies to existing architectures which lack enhanced safety concepts beyond common fail-safe systems. Especially, electronic components without...
Certification is the process in which a manufacturer has to prove to authorities that an aircraft and systems like safety-critical avionic systems work safely as intended without unacceptable hazards. Means to achieve this are redundancy, separation/protection, monitoring, and recovery mechanisms. The objective of this paper is to provide a cost-efficient solution for monitoring of Commercial Off-The-Shelf...
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