A new approach to an analog ultra-low power vision chip design is presented. The prototype chip performs low-level convolutional image processing algorithms in real time. The circuit is implemented in 0.35 µm CMOS technology, contains 64 × 64 SIMD matrix with embedded analogue processors APE (Analogue Processing Element). The photo-sensitive-matrix is of 2.2 µm × 2.2 µm size, giving the density of...
Financed by the National Centre for Research and Development under grant No. SP/I/1/77065/10 by the strategic scientific research and experimental development program:
SYNAT - “Interdisciplinary System for Interactive Scientific and Scientific-Technical Information”.