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A mixed signal vision chip has been designed in a 0.18um 1P6M process. The chip incorporates a 256×256 array of processing elements, each element including 7 analog registers and 14 digital storage cells. By the programmable reconfiguration of these read/write storage elements, a compact and powerful processor array is enabled. Configuration options include setting up an array-wide analog diffusion...
People rarely put in their papers the things that didn't work, the mistakes they made, and how they found out what went wrong. Such confessions can help others learn how to avoid similar mistakes. Twenty-six confessions were collected to form the bulk of this paper. Themes that arise are errors that result from not understanding the limitations of simulation tools in modeling physical reality, chip...
In this paper we present an implementation of the asynchronous/synchronous processor array (ASPA2) - a digital SIMD vision chip. The chip has been fabricated in a 0.18 μm CMOS process and comprises 80×80 array of pixel processors. The architecture of the chip is overviewed, the design of the processing cell is presented and implementation issues are discussed. At 75 MHz ASPA2 demonstrates 373 GOPS/W...
This paper presents a new algorithm for computing a distance transform, particularly suitable for massively parallel cellular processor arrays. The proposed Enhanced City Block Distance Transform (ECBDT) achieves good approximation to Euclidean distances, operating with 'increment' and 'minimum' operations only, and requiring only local 4-neighbour communication. The distance values are calculated...
We studied neuromorphic models of binocular disparity processing and mapped them onto a vision chip containing a massively parallel analog processor array. Our goal was to make efficient use of the available hardware while preserving the fundamental computations performed by the models. We also developed an optical fixture that used mirrors to simultaneously focus two images onto the vision chip....
In image processing the tasks of rotating, mirroring and scaling the image are often required. These operations necessitate data transfer between distant elements in the image. SIMD processor arrays commonly support communication within the direct neighborhood only. In this paper a method for implementing long-distance data communication is proposed. Inspired by lattice gas cellular automata models...
We describe a robotic system consisting of an arm and an active vision system learns to align its sensory and motor maps so that it can successfully reach the tip of its arm to touch the point where it is looking. This system uses an unsupervised Hebbian learning algorithm, and learns the alignment by watching its arm waving in front of its eyes. After watching for 25 minutes, the maps are sufficiently...
This paper proposes a silicon neuron circuit which uses a slow-variable controlled leakage term to extend the repertoire of spiking patterns achievable in an integrate and fire model. The simulations reveal the potential of the circuit to provide a wide variety of neuron firing patterns observed in neocortex, including adapting and non-adapting, regular spiking, fast spiking, bursting, chattering,...
This paper presents the design of a vertically-integrated image sensor/processor device, implemented in a fully stacked 3-layer three-dimensional (3D) silicon on insulator (SOI) 150nm CMOS technology. This prototype 'vision chip' contains a 32 times 32 pixel-parallel processor array. Three silicon layers contain current-mode image sensors, current-mode analogue circuits and digital logic circuits,...
FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biological neuron/synaptic models. Also their routing structures cannot accommodate the high levels of neuron inter-connectivity inherent in complex SNNs. This paper...
We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software is used to explore algorithms that are designed for CPAs, neuromorphic arrays, multi-layer neural networks and vision chips. The software (APRON) uses a highly optimised core combined with a flexible compiler to provide the user with tools for the prototyping of new array hardware and...
A software tool for the development, prototyping and emulation of cellular processor array hardware is presented. APRON provides a dasiavirtual processor arraypsila that operates at high speed, that can be extended to form vision systems, multi-layer neural networks, cellular neural networks and neuromorphic arrays.
Algorithms designed for machine vision applications such as medical imaging, surveillance, etc., very often require some kind of comparison between images. The non-linear wave metric can measure both the shape and the area difference between two objects in one single operation. We present the implementation of the wave metric on the SCAMP chip that combines the benefits of a highly selective metric...
In this paper a new technique for segmenting and tracking moving objects in a user-defined control area is presented. It is based on an active contours technique called pixel-level snakes (PLS) whose capabilities to manage changes of contour topology and to introduce additional constraints in the contour evolution are used to define a control area as well as to segment and track moving objects. Furthermore,...
This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 mum CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking...
In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits from full programmability (discrete-time mode) and high operational performance in global image processing operations (continuous-time mode) thus extending the application field of smart sensors from low- to medium-level processing...
The influence of rapid thermal annealing on the dielectric properties of BaHfO3 high-k dielectric layers was investigated. Annealing treatment at elevated temperatures (~ 800degC) results in a significant increase of the dielectric constant and capacitance density with respect to the untreated films. This result is correlated with the transition from amorphous to the crystalline cubic perovskite structure...
We present a new approach to execution of global image processing operations on massively parallel cellular processor arrays. Combining conventional synchronous processing with simple asynchronous propagations we achieve performance increase on global operations without additional hardware cost. By the example of watershed transformation we demonstrate the benefits of mixed synchronous/ asynchronous...
In this paper, a pixel-parallel image sensor/processor architecture with a fine-grain massively parallel SIMD analogue processor array is overviewed and the latest VLSI implementation, SCAMPS vision chip, comprising 128 times 128 array, fabricated in a 0.35mum CMOS technology, is presented. Examples of real-time image-processing executed on the chip are shown. Sensor-level data reduction, wide dynamic...
The paper presents a silicon neuron circuit that mimics the behaviour of known classes of biological neurons. The circuit has been designed in a 0.35 mum CMOS technology. The firing patterns of basic cell classes: regular spiking (RS), fast spiking (FS), chattering (CH) and intrinsic bursting (IB) are obtained with a simple adjustment of two biasing voltages. The simulations reveal the potential of...
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