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ESD sensitivity of silicon photonics critically affects manufacturability. We report the ESD sensitivity of monolithic silicon photonic elements, using ESDA/JEDEC tests. TiN heaters were class 1C, requiring JEDEC Basic ESD Control. Ge-photodiodes were class 0B, requiring Detailed ESD Control, unless on-chip ESD solutions are implemented.
This paper reports new accurate and scalable behavioral modeling for novel 3D field-programmable ESD protection circuits using Verilog-A, which enables post-Si on-chip and insystem ESD protection design simulation and verification. New field-programmable ESD protection devices were fabricated in CMOS-compatible processes utilizing SONOS and nano crystal dots structures. The ESD behavior models were...
Robust on-chip ESD protection without RF performance degradation is a challenge in RF IC designs. This paper reviews a new co-design technique for ultra wideband (UWB) RF ICs and ESD protection so as to achieve whole-chip design optimization.
We report a new nano-switching ESD protection mechanism and dual-polarity Cu/SixOyNz/W nano crossbar array ESD structures. Experiments show full ESD protection featuring fast response of 100pS ultra low leakage of <2pA and ESD protection of >9A. New dispersed local ESD tunneling model and CMOS integration are reported.
We report design and analysis of full-chip ESD protection solution for high-voltage (HV) mixed-signal ICs in a BCD30V technology by mixed-mode ESD simulation involving integrated process, device, circuit and layout co-design. The full-chip HV ESD protection scheme includes both I/O and power clamp ESD protection. Mixed-mode ESD simulation technique enables pre-Si ESD design optimization and prediction...
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