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In recent years, the medical device industry has experienced a rapid increase in the complexity of algorithms that are being developed for new therapy modalities. Traditional software specification and development processes are poorly suited for such complex algorithms and may result in excessive development costs and protracted schedules.
Deep Neural Networks (DNNs) have emerged as a powerful and versatile set of techniques showing successes on challenging artificial intelligence (AI) problems. Applications in domains such as image/video processing, autonomous cars, natural language processing, speech synthesis and recognition, genomics and many others have embraced deep learning as the foundation. DNNs achieve superior accuracy for...
Emerging applications require computing platforms to extract task-relevant information from increasingly large amounts of data. These requirements place stringent constraints on energy efficiency, throughput, latency, and for certain data types, security and privacy of computing platforms. Traditionally, silicon CMOS scaling has been relied upon to meet these energy and delay constraints. However,...
The next generation of cellular wireless communication networks (the much hyped “5G”) is targeting a 1000x increase in data capacity. This has sparked an investigation of new and transformative wireless communication paradigms, including massive MIMO, full duplex and millimeter-wave wireless. These new wireless paradigms place requirements on the radio circuitry that are orders of magnitude more challenging...
For the design and verification of a heterogeneous system architecture containing analog, digital, and software functionality, the use of modern languages and advanced Electronic System-Level (ESL) top-down design methodologies becomes fundamental. This paper will present the industrial application of the SystemC analog/mixed-signal (AMS) extensions in combination with SystemC and other C++ libraries,...
With low power and variation-tolerant features, asynchronous have been widely used in advanced VLSI designs. Testing asynchronous circuits has become a very important practical issue. This research presents new test methodology, including design for testability (DFT) and automatic test pattern generation (ATPG), for asynchronous dual-rail circuits. The proposed DAC-scan cell is a hazard-free scan...
As VLSI technology scales to deep sub-micron, design for interconnections becomes increasingly challenging. The traditional bus routing follows a sequential bit-by-bit order, and few works explicitly target inter-bit regularity for signal groups via multi-layer topology selection. To overcome these limitations, we present Streak, an efficient framework that combines topology generation and wire synthesis...
Recent NAND flash devices have large page sizes. Although large pages are useful in increasing the flash capacity, they can degrade both the performance and lifetime of flash storage systems when small writes are dominant. We propose a new NAND programming scheme, called erase-free subpage programming (ESP), which allows the same page to be programmed multiple times for small writes. By avoiding internal...
Due to their safety-critical nature, cyber-physical systems (CPS) must tolerate faults and security attacks to remain fail-operational. However, conventional techniques for improving safety, such as testing and validation, do not meet this requirement, as shown by many of the real-world system failures in recent years, often with major economic and public-safety implications. We aim to improve the...
Redundant Multi-Threading (RMT) provides a potentially low cost mechanism to increase GPU reliability by replicating computation at the thread level. Prior work has shown that RMT's high performance overhead stems not only from executing redundant threads, but also from the synchronization overhead between the original and redundant threads. The overhead of inter-thread synchronization can be especially...
To reduce clock power, we present a novel timing-driven incremental multi-bit register (MBR) composition methodology for designs that may be rich in MBRs after logic synthesis. It identifies nearby compatible registers that can be merged without degrading timing, and without reducing the “useful clock skew” potential. These registers are merged providing the MBR placement can be legalized according...
Kinematics is the basis of robotic control, which manages the robots' movement, walking and balancing. As a critical part of Kinematics, the Inverse Kinematics (IK) will consume more time and energy to figure out the solution with the degrees of freedom increase. It goes beyond the ability of general-purpose processor based methods to provide real-time IK solver for manipulators with high degree of...
Despite being employed in burgeoning efforts to improve power delivery efficiency, integrated voltage regulators (IVRs) have yet to be evaluated in a rigorous, systematic, or quantitative manner. To fulfill this need, we present Ivory, a high-level design space exploration tool capable of providing accurate conversion efficiency, static performance characteristics, and dynamic transient responses...
Recent research has demonstrated promising results in solving constrained satisfaction problem (CSP) using D-Wave quantum annealer. However, the embedding of the CSP suffers drawbacks such as long embedding time in addition to poor quality due to long chains that reduce the ground state probability. To address those issues, we propose an effective embedding technique that reduces the embedding time...
The Pauli frame mechanism allows Pauli gates to be tracked in classical electronics and can relax the timing constraints for error syndrome measurement and error decoding. When building a quantum computer, such a mechanism may be beneficial, and the goal of this paper is not only to study the working principles of a Pauli frame but also to quantify its potential effect on the logical error rate. To...
A wide variety of error tolerant applications supports the use of approximate circuits that achieve power savings by introducing small errors. This paper proposes a fast and novel algorithm for the design of such circuits with the goal of maximizing power savings, constrained by a fixed error budget, through an analytical expression to optimally select the number of bits to be approximated. This algorithm...
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