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AI, Robotics, and loT are attracting wide attention, expected as technologies to change society in the future. These innovative technologies have potentials to build (1) a borderless communication society, (2) a symbiotic society between humans and robots, and (3) a safe and secure networked society. This paper describes some specific solutions by Panasonic: (1) automatic translation solution, (2)...
Waymo's self-driving cars contain a broad set of technologies that enable our cars to sense the vehicle surroundings, perceive and understand what is happening in the vehicle vicinity, and determine the safe and efficient actions that the vehicle should take. Many of these technologies are rooted in advanced semiconductor technologies, e.g. faster transistors that enable more compute or low noise...
A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10–102 and 102–104 times better than a CPU/GPU/FPGA.
An energy-efficient hybrid neural network (NN) processor is implemented in a 65nm technology. It has two 16×16 reconfigurable heterogeneous processing elements (PEs)arrays. To accelerate a hybrid-NN, the PE array is designed to support on demand partitioning and reconfiguration for parallel processing different NNs. To improve energy efficiency, each PE supports bit-width adaptive computing to meet...
We present a heterogeneous microprocessor for IoE sensor-inference applications, which achieves programmability required for feature extraction strictly using application data. Acceleration, though key for energy efficiency, poses substantial programmability challenges. These are overcome by exploiting genetic programming (GP) for automatic program synthesis. GP yields highly structured models of...
A digital-analog hybrid neural network exploits efficient analog computation and digital intra-network communication for feature extraction and classification. Taking advantage of the inherently low SNR requirements of the Locally Competitive Algorithm (LCA), the internally-analog neuron is 3x smaller and 7.5x more energy efficient than an equivalent digital design. This work demonstrates large-scale...
A compact and low-power digital-domain noise coupling technique is proposed for higher-order CT DSM implementation, exploiting the architectural advantage of a SAR ADC and a simple digital filter. With an 8b SAR ADC and a second-order digital noise coupling filter, a prototype fourth-order DSM achieves 74.4dB SNDR for 10MHz BW with an OSR of 16 in a 28nm CMOS, showing an FoMs_dr of 174.5dB.
This paper presents an OTA-less 2nd-order VCO-based CT ΔΣ modulator featuring a passive integrator that makes use of the VCO's inherent parasitic effect. A low-power capacitive feedback technique is also presented for robust loop compensation. Fabricated in 40nm CMOS, the prototype occupies 0.028mm2 of active area and consumes 524μW when sampling at 330MHz. The ΔΣM achieved peak Walden FoM of 19.8fJ/step...
Conventional dynamic element matching limits the continuous time ΣΔ ADC architecture at high speeds. This work introduces a Time-Interleaved Reference Data-Weighted-Averaging (TI-RDWA) architecture that breaks the speed limitation of the traditional DEM decoder. Time-interleaving eliminates the reference voltage settling bottleneck, enabling DWA operation at 5 GHz, while still achieving the benefits...
This paper presents a 3rd order single-bit CT ΔΣ modulator with active-RC integrators using negative-R assistant at virtual ground, which mitigates opamp's requirements including the thermal noise and linearity leading to a drastic power-saving. Fabricated in a 65nm CMOS process, the modulator occupies area of 0.27mm2. It achieves 100.5dB SFDR and 93.1dB DR in 20kHz BW, while consuming only 55μW from...
This paper presents a 16-channel closed-loop neuromodulation SoC for human seizure control. The SoC includes a 16-ch signal acquisition unit, a bio-signal processor, a 16-ch adaptive stimulator, and wireless telemetry. The signal acquisition unit achieves 3.78 NEF and shares electrodes with stimulator. The seizure detection latency is 0.76s and delivered 0.5–3mA biphasic current stimulation. The SoC...
In this paper, a bone-guided cochlear implant (BGCI) SOC microsystem is proposed and designed. The BGCI microsystem uses four or more electrodes placed on the bone surface of the cochlea and one on the round window to preserve partially the acoustic hearing. The external SOC of the BGCI processes the acoustic signals and generates stimulation patterns and command that are transmitted to the implanted...
We present an 180nm HV CMOS IC for concurrent neural stimulation and recording that combines 64 low-noise recording front-ends and 4 independent stimulators multiplexed to any of the 64 channels. The stimulators have 5mA peak current, 12V compliance and dynamic power management to maximize efficiency. Co-design of the stimulation and recording subsystems resulted in 100mV of recording linear range,...
Advanced bionic prosthetics that can restore both the motor functionality and sensory perception of an amputee, require high-resolution recording and stimulation interfaces targeting the peripheral nervous system (PNS). To provide high nerve fiber selectivity, we propose a low-noise (3.67μVrms) low-power (2.24mW) and high-density CMOS microelectrode probe for intra-neural implantation. The probe is...
We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single transmitter (TX) broadcasts NRZ data to eight receivers (RXs) distributed along an on-chip RC-dominated 10mm-long channel. The TX comprises a full-rate AC-coupled 2-tap FIR driver with a quarter-rate pre-driver. Each RX is equipped with a novel decision-gated 1-tap speculative DFE optimized for low-power....
An all-digital 2-tap half-rate time-based decision feedback equalizer (TB-DFE) was demonstrated on a 10mm on-chip serial link. Implemented in a 65nm GP technology, the transmitter and receiver achieve an energy-efficiency of 31.9 and 45.3 fJ/b/mm, respectively, at a data rate of 10Gb/s. A Bit Error Rate (BER) less than 10−12 was verified for an eye width of 0.43 Unit Interval (UI) using an in-situ...
An FFE TX which automatically adapts impedance to arbitrary channel and RX impedances is proposed. Based on on-chip TDR monitoring, the TX impedance matching is adaptively relaxed without increasing reflection. In experiment, the proposed TX adapted to any combination of 35–75Ω channels and 30–200Ω RX impedances, achieving 3.8x eye improvement and the maximum data rate of 12Gb/s.
A distance-immune inductively coupled link is based on a free-running oscillator tuned by coupled resonators. It can transfer data at up to 4 Mbps and 2 Mbps in half duplex with an LSK uplink and ASK downlink, respectively (at BER< 5 × 10−8). In uplink direction, the implanted unit consumes less than 0.1 pJ/bit while transmitting.
This paper presents the fastest and most energy efficient body channel communication transceiver integrated into the smallest chip area. To enhance data rate with limited human body channel bandwidth, decision feedback equalization technique is adopted to body channel communication for the first time. The transceiver, fabricated in 65 nm CMOS technology, reliably (BER < 10−6) achieves the maximum...
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