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Asynchronous quasi-delay-insensitive (QDI) circuits are a promising solution for coping with aggressive process variations faced by modern technologies, as they can gracefully accommodate gate and wire delay variations. Furthermore, due to their inherent robustness, such circuits are also promising for deep voltage scaling applications, where delays are orders of magnitude larger. However, QDI design...
Integrated digital circuits are frequency capped by its heavily constrained paths between flip-flop stages. These so-called critical paths are highly susceptible to delay fluctuations leading designers to use guard-banding in order to avoid timing violations. Several effects can cause these variations, whereas aging is of rising importance. Many works have addressed this issue through monitoring of...
In beyond silicon research, Quantum-dot Cellular Automata (QCA) emerged as a candidate for replacing the traditional CMOS logic circuits. QCA is a paradigm based on the exchange of information between cells that takes advantage of Coulomb's law. In this work, we managed to extract dependence relations through a circuit designed on QCA Designer simulator. We built small models representing fragments...
Physical design tools must handle huge amounts of data in order to solve problems for circuits with millions of cells. Traditionally, Electronic Design Automation tools are implemented using Object-Oriented Design. However, using this paradigm may lead to overly complex objects that result in waste of cache memory space. This memory wasting harms cache locality exploration and, consequently, degrades...
This work presents a hardware implementation of the morphological reconstruction algorithm for biomedical images analysis. The morphological reconstruction algorithm is based on the Sequential Reconstruction (SR). In this case. a hardware architecture has been developed and implemented by mapping the SR algorithm into an Altera Cyclone IV E FPGA based platform. including a NIOS II processor. The developed...
This paper describes novel integrated transmission lines base on slotted-floating shield for ultra-wide band operation a millimeter-wave frequencies. The designed structures con sist of two main conductors used for signal and ground along with a floating conductor, which improves the per formance of the line. The implemented designs increase th line-impedance and reduce the wavelength of the guided...
This paper presents a wideband CMOS FDSOI fully-balanced analog multiplier which is part of a magnitude calculator for real-time spectrum sensing. Simulations based on a 28nm CMOS FDSOI technology show that the proposed multiplier offers 13.8GHz bandwidth when loaded by a high capacitance with a power consumption of 343mW under a IV supply. Multiplication between high frequency voltage samples satisfy...
Internet of Things (IoT) is a topic of growing interest and intensive research in industry, technological centers and academy, where data communication is one of its most relevant aspects. Since IoT is an open field for new applications, it does not have yet a standard communication protocol. This paper presents the system level design of a WiFi receiver supporting the novel low power standard IEEE...
The increasing resolutions combined with storage and processing limitations of mobile devices point to the need for new compression techniques for video coding. Meanwhile, to achieve higher compression rates without compromising quality, the coding process becomes more and more complex. In reference software of HEVC the most time consuming step is the execution of Motion Estimation (ME), which is...
A 10-bit single-channel SAR ADC is designed in a 130nm CMOS technology. An original DAC is proposed, merging a binary-weighted structure and a C/2C topology in order to reduce overall energy consumption. A built-in calibration circuit improves the conversion accuracy. The proposed SAR ADC samples at 6.66MHz, achieving a SNDR of 49.78 dB for a 1MHz input signal (ENOB of 8 bits). The simulated INL is...
This work proposes a secure Network-on-Chip (NoC) approach, which enforces the encapsulation of sensitive traffic inside the asymmetrical security zones while using minimal and non-minimal paths. The NoC routing guarantees that the sensitive traffic communicates only through trusted nodes, which belong to a security zone. As the shape of the zones may change during operation, the sensitive traffic...
Operating CMOS circuits at subthreshold supply voltages is an attractive solution for substantial energy reduction, at the expense of strong timing performance degradation, for a broad range of battery operated appliances. One of the challenges of this approach in current technology nodes is the reduced available noise margin when operating at low supplies. This paper evaluates the Static Noise Margin...
Digital circuit technologies at nanoscale levels increase the likelihood of permanent, transient and intermittent faults. As a result, the demand for fault tolerance strategies is the main subject of many types of research targeting System-on-Chip (SoC) designs. In particular, retransmission mechanisms are one of the most used solutions in the Network-on-Chip (NoC) operation, but these mechanisms...
Many-core architectures are similar to a computer network, where it is necessary to ensure the security during the execution of sensitive applications. This article discusses two security-related issues: the secure admission of applications and the prevention of resource sharing during their execution. The safe application admission is an open research subject for many-core systems. Although several...
This paper evaluates the efficiency and performance impact of a dual-core lockstep as a method for fault-tolerance running on top of FreeRTOS applications. The method was implemented on a dual-core ARM Cortez-A9 processor embedded into the Zynq-7000 APSoC. Fault injection experiments show that the method can mitigate up to 63% on the FreeRTOS applications. This result is very near to the mitigation...
The HEVC is one of the most recent video coding standards, developed in order to face upcoming challenges, due to higher video quality and resolution. One of the HEVC components is the entropy encoder, which consists only of the Context Adaptive Binary Arithmetic Coding (CABAC) algorithm. The CABAC algorithm imposes some severe difficulties in order to achieve increasing throughput, due to the high...
The demand for higher quality video has increased in the past few years, due to the huge amount of electronic devices that process digital video in even higher resolutions. For that purpose, video coding techniques are used, which have, as main goal, the reduction of the required representation to process a digital video. Furthermore, embedded hardware video solutions are sought for both industry...
The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. System-on-chip (SoC) applications in the automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 0C. This work proposes an analysis of latched-comparators...
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