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Various industry forecasts project that, by 2020, there will be around 50 billion devices connected to the Internet of Things (IoT), helping to engineer new solutions to societal-scale problems such as healthcare, energy conservation, transportation, etc. Most of these devices will be wireless due to the expense, inconvenience, or in some cases, the sheer infeasibility of wiring them. Further, many...
DRAM consumes a significant amount of energy in mobile computing devices today. Emerging non-volatile memory such as magnetoresistive memory (MRAM) offers a DRAM alternative and can potentially lead to a more energy-efficient memory system. The MRAM technology is already mature, but considering the memory industry is highly standardized, we are still unable to see any MRAM used in mainstream products...
Speculative adders divide addition into subgroups and execute them in parallel for higher execution speed and energy efficiency, but at the risk of generating incorrect results. In this paper, we propose a lightweight correlation-aware speculative addition (CASA) method, which exploits the correlation between input data and carry-in values observed in real-life benchmarks to improve the accuracy of...
The design complexity of modern high performance processors calls for innovative design techniques and methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets. This paper describes new processor design and optimization approaches that bridge the gap between high performance and...
In a gate-level monolithic 3D IC (M3D), all the transistors in a single logic gate occupy the same tier, and gates in different tiers are connected using nano-scale monolithic inter-tier vias. This design style has the benefit of the superior power-performance quality offered by flat implementations (unlike block-level M3D), and zero total silicon area overhead compared to 2D (unlike transistor-level...
JavaScript has become a general-purpose programming environment that enables complex, media-rich web applications. An increasing number of JavaScript programs are parallelized to run efficiently on today's multicore CPUs, which are capable of dynamic core scaling (DCS) and voltage/frequency scaling (DVFS). However, significant power savings are still left on the table since an operating point (in...
The recent successful integration of magnetic racetrack memory forecasts a new computing era with unprecedentedly high-density on-chip storage. However, racetrack memory accesses require frequent magnetic domain shifting, introducing overheads in access latency and energy consumption. In this paper, we evaluate and compare several different physical layout strategies and array organizations. From...
Planar UTBB FD-SOI technology is an opportunity for energy efficient SOCs in deeply scaled technologies. Thanks to its excellent responsiveness to power management design techniques, this technology brings a significant improvement in terms of performance and power savings. The unique features offered by this technology at process and design levels enable a differentiation in terms of flexibility,...
Voltage noise is a major obstacle in improving processor energy efficiency because it necessitates large operating voltage guardbands that increase overall power consumption and limit peak performance. Identifying the leading root causes of voltage noise is essential to minimize the unnecessary guardband and maximize the overall energy efficiency. We provide the first-ever modeling and characterization...
A clock tree typically consumes substantial dynamic power, and thus the considerable heat generated by itself can cause serious clock-skew variations. In this paper, we propose a self-heating-aware buffered clock tree synthesis flow. A mixed integer linear programming (MILP) formulation is proposed to simultaneously model heat spreading, place buffers, and determine a temperature-aware clock tree...
Smartphones are becoming increasingly energy-hungry to support feature-rich applications, posing a lot of pressure on battery lifetime and making energy consumption a non-negligible issue. In particular, DRAM is among the most demanding components in energy consumption. In this paper, we propose DR. Swap, an energy-efficient paging design to reduce energy consumption in smartphones. We adopt emerging...
We propose a general model for array-based approximate arithmetic computing to trade off accuracy for significant reduction in energy consumption, which is realized by identifying input signatures for efficient compensation of approximation errors. Under this model, our approximate 16×16 bits fixed-width Booth multiplier consumes 44.96% and 28.33% less energy and area compared with the most accurate...
To achieve high performance, conventional superscalar processors maintain maximum front-end instruction delivery bandwidth, which is often suboptimal when program behavior and priority metrics change. This paper proposes an adaptive front-end throttling technique that dynamically adjusts the front-end instruction delivery bandwidth as program behavior changes to optimize a target metric, being performance,...
Technology scaling enables the design of low cost biosignal processing chips suited for emerging wireless body-area sensing applications. Energy consumption severely limits such applications and memories are becoming the energy bottleneck to achieve ultra-low-power operation. When aggressive voltage scaling is used, memory operation becomes unreliable due to the lack of sufficient Static Noise Margin...
This work presents energy harvesting techniques from low-voltage current used to prevent galvanic corrosion between a metallic structure and a permanent copper/copper sulfate (Cu/CuSO4) reference electrode. Supercapacitors are adopted to compensate for or overcome the limitations of batteries. Then, a boost converter is used to convert the low voltage levels of galvanic corrosion to that needed by...
Frame refreshes, that are used to retain frame images from frame buffers for display subsystems in mobile devices, waste energy and memory bandwidth. In this paper, we propose an intelligent frame refresh mechanism to reduce redundant frame refreshes and useless data accesses to frame buffers, which bridges the semantic gap between frame buffers and frame refreshes, and exploits the knowledge of frame...
Power management for large last-level caches (LLCs) is important in chip-multiprocessors (CMPs), as the leakage power of LLCs accounts for a significant fraction of the limited on-chip power budget. Since not all workloads need the entire cache, portions of a shared LLC can be disabled to save energy. In this paper, we explore different design choices, from circuit-level cache organization to micro-architectural...
In-situ error-detection and correction techniques have a strong potential to eliminate the worst-case margins in ultra-low-voltage (ULV) pipelines while achieving high variation tolerance. Adding the capability of error detection, however, can incur large hardware overhead, especially in ULV due to the larger variability. In this paper, we analyze the hardware overhead of error-detection techniques...
Electrical energy systems (EESs) are systems which consume, generate, distribute and store energy at various scales. This paper presents a modeling and simulation framework that uses principles borrowed from the system-level simulation of digital systems and extends them to the case of EESs. The framework relies on open-source standards such as SystemC (and its Analog and Mixed-Signal extensions)...
Supercomputers, nowadays, aggregate a large number of nodes sharing the same nominal HW components (eg. processors and GPGPUS). In real-life machines, the chips populating each node are subject to a wide range of variability sources, related to performance and temperature operating points (i.e. ACPI p-states) as well as process variations and die binning. Eurora is a fully operational supercomputer...
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