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This paper presents a 1/4-rate PAM4 receiver employing a sampling decoder with an adaptive variable-gain rectifier (AVGR) to achieve a bit efficiency of 1.38 pJ/bit. By concurrently performing gain adaptation and amplitude rectification for decoding the least significant bit (LSB), the proposed decoder greatly reduces power consumption compared with the conventional full-rate topology using three...
This work presents a self-adaptation algorithm to automatically adjust the peaking settings of a continuous-time linear equalizer (CTLE) in a high-speed PAM4 receiver. A statistical approach is adopted to improve the robustness and flexibility of the adaptation algorithm. The PAM4 top level distribution around the peak value of several consecutive top levels guides the CTLE to attain the optimal digital...
This paper presents a source-synchronous receiver with a quarter-rate linear sampling phase detector (LSPD) with embedded FFE and DFE. The 1-tap FFE and 1-tap DFE are realized by reusing the data samples generated in the LSPD to minimize power and area overhead. The equalization is applied to both data and edge samples to suppress ISI for improving BER and bit efficiency. The 28-nm CMOS receiver IC...
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